SANKHYA Teraptor Processor Verification Solution Proposal

Processors are increasingly becoming the essential element for creating advanced ASICs, SoCs and FPGA designs or new data I/O controllers for the latest data transfer and storage technologies.
With the IoT, such designs are getting embedded into elements of every day life. Embedding a processor into a design brings a multitude of benefits - most importantly the ability to use the ASIC for different applications by changing the software. But, testing a processor is complex. It is easily the most complex of the blocks on a chip. Chip designs may have more than one processor (say a DSP or RISC) and even a network on chip with multiple cores. And they need to be bug free to run the OS installed on their hardware perfectly. One bug overlooked may eventually cost millions.

Teraptor SPVP

The Teraptor Synthetic Processor Verification Platform is an automated intent driven and formal verification framework which offers a processor modeling language (SMDL), automated test synthesis tools (Teraptor MSE), a meta-model driven assembler (Teraptor SDK) and simulator (Teraptor Player) along with convenient integration scripts (Teraptor Verifier). Teraptor SPVP allows ASIC teams to quickly put together a verification system for the embedded processor cores. Read the full proposal.

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