Modeling Cycle Information and Cycle Aware Simulation

    SANKHYA Teraptor supports modeling Plant/Domain Components (using C++), Processor Models (using SMDL) and System and System of System Models (using SSDL). The cycle level behavior of processors and devices can be specified using attributes provided by SMDL and SSDL. The cycle aware edition of Teraptor Player (which plays the models) enforces the cycle-level behavior during simulation. The performance of a system modeled with cycle information can be studied with different applications as well as for different settings of the cycle attributes, thereby covering a spectrum of hardware timings and system loads.  Read More...

Implementing segmented virtual memory support in a system model using MMU (TCC-MEM-MMU)

    The TCC-MEM-MMU component allows basic segmented memory to be modeled in an SSDL system. This technical note describes how to include MMU in your system.  Read More...

Sankhya Technologies - Technical Articles

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Processor Verification with Teraptor

    Transcript from Twitter Chat conducted at 12 Noon EST on October 28, 2013. Hash tag is #SoC.  
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