Processor Verification Using Teraptor Processor Verification Tool

An innovative approach to processor verification is possible with the use of the SMDL - Model Space Explorer and the Teraptor Processor Verification Tool.The innovation basically involves automating the generation of test sequences in a controlled manner to statistically increase the chances of a defect being detected.

About Processor Verification

A processor is often designed using a high level language like VHDL or Verilog. A typical processor design goes through several stages of simulation and synthesis (realization) before finally it is physically realized on an FPGA or Silicon.

At every stage there is a possibility for a defect (or more) to be introduced. This means that a processor design or realization needs to be verified at every stage.

The key logical verification for the processor consists of ensuring that the processor accurately computes the results of instructions conforming to the processor architecture.

Processor Verification - Challenges

A simple 16-bit, single-word-length, RISC processor will support 65,536 different instruction patterns (machine-codes). Assuming 16 registers, the core processor has approximately 65536 to-the-power-of 16 different states. Testing the processor behavior for all combinations of the processor states and single instruction programs is already impossible.

A pipelined processor with say 5 stages can be processing programs of upto 5 instructions simultaneously. Just testing a processor for all possible states and single instruction programs is insufficient to verify a processor against the architecture specification.

Even without considering the peripheral control registers and external memory state, it is obvious that processor verification using a brute force approach is beyond the computational power of the universe.

Processor Verification - Some Solutions

• A first solution for processor verification is to create a simple test plan and ensure that common instruction patterns and application programs work on the processor realization. This may be a reasonable option if there is a limited set of applications that will be running on the processor.
• A more complex solution for processor verification will involve building a large team of verification engineers to create large test plans consisting of various combinations of test cases planned to identify potential problems in the processor realization. This works well especially when there is no real limit on funding for the verification team.
• A different solution is to port existing verification suites to a new processor. By making the verification suites processor independent, a verification suite can be made to work with different processor designs. Off the shelf processor verification solutions are naturally expensive.
• The typical situation is that verification has to be done with a limited budget. A more realistic and competitive solution is clearly required. It is obvious that only an innovative solution that makes the verification cost a logarithmic function on the number of verification tests or makes the verification costant a constant can be both competitive and comprehensive enough for a specific application.

Complete Processor Verification Solution

SANKHYA Consulting offers complete processor verification solution for your processor architecture. This includes Teraptor Verifier, Model Space Explorer(MSE), Training, Mentoring and Application Engineering.

Next Steps

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